1. Field of the Invention
The present invention relates to a semiconductor device with a SALICIDE structure having a metal silicide selectively formed on a diffusion layer or the like. The present invention also relates to a method for manufacturing the above semiconductor device, and a heating apparatus for use in the manufacturing method.
2. Description of the Related Art
Conventionally, MOS type field effect transistors (FET) have been used as basic devices of an LSI. Improving the LSI performance demands higher performance of MOS transistors. To improve the transistors' performance, it is important to form a diffusion layer, such as source/drain regions, shallow.
A low-accelerating ion injection is widely used as a method for forming a diffusion layer of a MOS transistor. Recently, an impurity (e.g., As) diffusion method has also been used. The use of these methods can form shallow source/drain regions of an about 0.1 .mu. depth. With regard to the p+/n junction, it is possible to form shallow source/drain regions. More specifically, such shallow source/drain regions can be realized by injecting Si.sup.+, Ge.sup.+ or Sn.sup.+ ions to make the surface layer of an Si single crystal non-crystalline, then injecting BF.sub.2 ions at a low acceleration. In this case, it is possible to realize an about 0.1 .mu. depth even after a heat treatment to make the region active.
This diffusion layer having a depth of about 0.1 .mu. however has a high sheet resistance of 100 .OMEGA./.quadrature. or greater. Improving the speed of a semiconductor device therefore requires that the resistance be made smaller by rendering the surface of the diffusion layer metallic.
Recently, therefore, a study has been made on a so-called SALICIDE, a method of forming silicides on the surfaces of a polycrystal Si gate region and source/drain regions selectively and through self-alignment. According to this method, an insulative film is formed on the side wall of the polycrystal Si gate after formation of an impurity diffusion layer, metal such as titanium (Ti) is deposited on the entire surface of the substrate, subjecting this metal to heat treatment such as lamp annealing to make only the gate, drain and source regions silicide through self-alignment, then etching out that metal portion which has not been reacted.
TiSi.sub.2 (Ti silicide) is typically used to reduce the sheet resistance of the impurity diffusion layer. TiSi.sub.2, however, has the following shortcomings, as disclosed in Chih-Shih Wei, Gopal Raghavan, M. Lawrence A. Dass, Mike Frost, Teodoro Brat and David B. Fraster, VMIC Conference, p. 241-p 250, Jun. 12-13, 1989.
First, the film stress of TiSi.sub.2 is tensile and has a value of 2 to 2.5.times.10.sup.10 dynes/cm.sup.2. The high stress in TiSi.sub.2 tends to introduce more defects in the Si substrate. These defects may degrade the junction integrity.
Second, because Si is the diffusing species during TiSi.sub.2 formation, it tends to diffuse from gate and S/D regions into the Ti overlayer and to form a silicide bridge over the spacer regions resulting in a gate-S/D shorting problem.